After consistently providing large improvements in productivity and performance for more than two decades, CMOS is expected to approach its physical limits in the coming decade. To enable future technology scaling, intensive research is being directed towards the development of nanoscale molecular devices, such as carbon nanotube and nanowire. Such nanodevices demonstrate superior characteristics over MOSFET in terms of integration density, performance, power consumption, etc. However, lack of a mature fabrication process is a roadblock in implementing chips using these nanodevices. If photo-lithography could be used to implement structures made from these nanodevices, then such structures could be combined with CMOS logic to create hybrid CMOS/nanochips, which could leverage the beneficial aspects of both technologies.
Motivated by the impressive potential of nanotechnologies, researchers are investigating nanoelectronic circuits and architectures. If such circuits/architectures are implemented using bottom-up chemical self-assembly techniques, then the chip defect levels are expected to be high (between 1% and 10%). To be able to deal with such high defect levels, regular architectures are favored. Reconfigurable architectures, in addition to being regular, allow reconfiguration around fabrication defects as well as run-time faults. Thus, both regular and reconfigurable architectures have found popularity.